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24AA014/24LC014
1K I2CTM Serial EEPROM
Device Selection Table
Part Number 24AA014 24LC014 VCC Range Max Clock Temp. Range I I
Package Types
PDIP/SOIC A0 A1 A2 VSS TSSOP/MSOP A0 A1 A2 VSS 1 2 3 4 8 7 6 5 1 8 VCC WP SCL SDA
24AA014 24LC014
1.8V - 5.5V 400 kHz(1) 2.5V - 5.5V 400 kHz
2 3 4
7 6 5
Note 1: 100 kHz for VCC < 2.5V
Features
* Single-supply with operation down to 1.8V * Low-power CMOS technology - 1 mA active current, typical - 1 A standby current typical at 5.5V * Organized as a single block of 128 bytes (128 x 8) * Hardware write protection for entire array * 2-wire serial interface bus, I2CTM compatible * 100 kHz and 400 kHz clock compatibility * Page write buffer for up to 16 bytes * Self-timed write cycle (including auto-erase) * 10 ms max. write cycle * Address lines allow up to eight devices on bus * 1,000,000 erase/write cycles * ESD protection > 4,000V * Data retention > 200 years * 8-pin PDIP, SOIC, TSSOP and MSOP packages * Available for extended temperature ranges - Industrial (I): -40C to +85C
24AA014 24LC014
VCC WP SCL SDA
Block Diagram
A0 A1 A2 I/O Control Logic WP HV Generator
Memory Control Logic
XDEC
EEPROM Array
SDA SCL VCC VSS Write-Protect Circuitry YDEC Sense Amp. R/W Control
Description
The Microchip Technology Inc. 24AA014/24LC014 is a 1 Kbit Serial Electrically Erasable PROM with operation down to 1.8V. The device is organized as a single block of 128 x 8-bit memory with a 2-wire serial interface. Low current design permits operation with typical standby and active currents of only 1 A and 1 mA, respectively. The device has a page write capability for up to 16 bytes of data. Functional address lines allow the connection of up to eight 24AA014/24LC014 devices on the same bus for up to 8 Kbits of contiguous EEPROM memory. The device is available in the standard 8-pin PDIP, 8-pin SOIC (150 mil), TSSOP and MSOP packages.
Pin Function Table
Name VSS SDA SCL VCC A0, A1, A2 WP Ground Serial Data Serial Clock Power Supply Chip Selects Hardware Write-Protect Function
2003 Microchip Technology Inc.
DS21809B-page 1
24AA014/24LC014
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings ()
VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65C to +150C Ambient temperature with power applied ................................................................................................-65C to +125C ESD protection on all pins ...................................................................................................................................................... 4 kV NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
VCC = +1.8V to +5.5V Industrial (I): TA = -40C to +85C Symbol VIH VIL VHYS VOL ILI ILO CIN, COUT ICC Read ICC Write ICCS Min. 0.7 VCC -- 0.05 VCC -- -- -- -- -- -- -- Max. -- 0.3 VCC -- 0.40 1 1 10 1 3 1 Units V V V V A pF mA mA A (Note 1) IOL = 3.0 mA, VCC = 4.5V IOL = 2.1 mA, VCC = 2.5V VIN = 0.1V to 5.5V, WP = Vss VOUT = 0.1V to 5.5V VCC = 5.0V (Note 1) TA = 25C, f = 1 MHz VCC = 5.5V, SCL = 400 kHz VCC = 5.5V VCC = 5.5V, SDA = SCL = VCC WP = VSS, A0, A1, A2 = VSS Conditions
All parameters apply across the specified operating ranges unless otherwise noted. Parameter SCL and SDA pins: High-level input voltage Low-level input voltage Hysteresis of Schmitt Trigger inputs Low-level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current Standby current
Note 1: This parameter is periodically sampled and not 100% tested.
DS21809B-page 2
2003 Microchip Technology Inc.
24AA014/24LC014
TABLE 1-2: AC CHARACTERISTICS
Vcc = 1.8V to 5.5V Industrial (I): TA = -40C to +85C All parameters apply across the specified operating ranges unless otherwise noted.
Parameter Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time Start condition hold time Start condition setup time Data input hold time Data input setup time Stop condition setup time Output valid from clock Bus free time
Vcc = 1.8V - 5.5V Vcc = 2.5V - 5.5V STD MODE FAST MODE Symbol Min. FCLK THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF -- 4000 4700 -- -- 4000 4700 0 250 4000 -- 4700 Max. 100 -- -- 1000 300 -- -- -- -- -- 3500 -- Min. -- 600 1300 -- -- 600 600 0 100 600 -- 1300 Max. 400 -- -- 300 300 -- -- -- -- -- 900 --
Units kHz ns ns ns ns ns ns ns ns ns ns ns
Remarks
(Note 1) (Note 1) After this period, the first clock pulse is generated Only relevant for repeated Start condition (Note 2)
TOF -- 250 20 +0.1 250 ns Output fall time from VIH minimum to VIL maximum CB -- 50 -- 50 ns (Note 3) Input filter spike suppression TSP (SDA and SCL pins) -- 10 -- 10 ms Byte or Page mode Write cycle time TWC Endurance 1M -- 1M -- cycles 25C, (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total EnduranceTM Model which can be downloaded at www.microchip.com.
(Note 2) Time the bus must be free before a new transmission can start (Note 1), CB 100 pF
FIGURE 1-1:
BUS TIMING DATA
TF THIGH TR
SCL
TSU:STA TLOW THD:DAT TSU:DAT TSU:STO
SDA IN
TSP
THD:STA TBUF
TAA SDA OUT
2003 Microchip Technology Inc.
DS21809B-page 3
24AA014/24LC014
2.0
2.1
PIN DESCRIPTIONS
SDA Serial Data
3.0
FUNCTIONAL DESCRIPTION
This is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open drain terminal. Therefore, the SDA bus requires a pull-up resistor to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.
The 24AA014/24LC014 supports a bidirectional, 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device that generates the serial clock (SCL), controls the bus access and generates the Start and Stop conditions while the 24AA014/24LC014 works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated.
2.2
SCL Serial Clock
The SCL input is used to synchronize the data transfer to and from the device.
2.3
A0, A1, A2
The levels on the inputs A0, A1 and A2 are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. Up to eight 24AA014/24LC014 devices may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either VCC or VSS.
2.4
WP
WP is the hardware write-protect pin. It must be tied to VCC or VSS. If tied to VCC, the hardware write protection is enabled. If the WP pin is tied to VSS the hardware write protection is disabled.
2.5
Noise Protection
The 24AA014/24LC014 employs a VCC threshold detector circuit that disables the internal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SCL and SDA inputs have Schmitt Trigger and filter circuits that suppress noise spikes to assure proper device operation even on a noisy bus.
DS21809B-page 4
2003 Microchip Technology Inc.
24AA014/24LC014
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1). The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device and is, theoretically, unlimited, though only the last sixteen will be stored when doing a write operation. When an overwrite does occur, it will replace data in a first-in first-out fashion.
4.1
Bus not Busy (A)
4.5
Acknowledge
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
Each receiving device, when addressed, is required to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: The 24AA014/24LC014 does not generate any Acknowledge bits if an internal programming cycle is in progress.
A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal.
The device that acknowledges has to pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the Stop condition (Figure 4-2).
FIGURE 4-1:
SCL (A) (B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
(C) (D) (C) (A)
SDA
START CONDITION
ADDRESS OR DATA ACKNOWLEDGE ALLOWED TO CHANGE VALID
STOP CONDITION
FIGURE 4-2:
ACKNOWLEDGE TIMING
Acknowledge Bit
SCL
1
2
3
4
5
6
7
8
9
1
2
3
SDA
Data from transmitter Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data.
Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data.
2003 Microchip Technology Inc.
DS21809B-page 5
24AA014/24LC014
5.0 DEVICE ADDRESSING
FIGURE 5-1: CONTROL BYTE FORMAT
Read/Write Bit Chip Select Bits 0 A2 A1 A0 R/W ACK A control byte is the first byte received following the Start condition from the master device (Figure 5-1). The control byte consists of a four-bit control code; for the 24AA014/24LC014 this is set as `1010' binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The chip-select bits allow the use of up to eight 24AA014/ 24LC014 devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are in effect the three Most Significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to a one, a read operation is selected. When set to a zero, a write operation is selected. Following the Start condition, the 24AA014/ 24LC014 monitors the SDA bus, checking the control byte being transmitted. Upon receiving a `1010' code and appropriate Chip Select bits, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24AA014/24LC014 will select a read or write operation.
Control Code S 1 0 1
Slave Address Start Bit Acknowledge Bit
5.1
Contiguous Addressing Across Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to expand the contiguous address space for up to 16K bits by adding up to eight 24AA014/24LC014 devices on the same bus. In this case, software can use A0 of the control byte as address bit A8, A1 as address bit A9 and A2 as address bit A10. It is not possible to sequentially read across device boundaries.
DS21809B-page 6
2003 Microchip Technology Inc.
24AA014/24LC014
6.0
6.1
WRITE OPERATIONS
Byte Write
Following the Start signal from the master, the device code(4 bits), the Chip Select bits (3 bits) and the R/W bit (which is a logic low) are placed onto the bus by the master transmitter. The device will acknowledge this control byte during the ninth clock pulse. The next byte transmitted by the master is the word address and will be written into the address pointer of the 24AA014/ 24LC014. After receiving another Acknowledge signal from the 24AA014/24LC014, the master device will transmit the data word to be written into the addressed memory location. The 24AA014/24LC014 acknowledges again and the master generates a Stop condition. This initiates the internal write cycle and the 24AA014/24LC014 will not generate Acknowledge signals during this time (Figure 6-1). If an attempt is made to write to the protected portion of the array when the hardware write protection has been enabled, the device will acknowledge the command but no data will be written. The write cycle time must be observed even if write protection is enabled.
The higher order four bits of the word address remain constant. If the master should transmit more than 16 bytes prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure 6-2). If an attempt is made to write to the protected portion of the array when the hardware write protection has been enabled, the device will acknowledge the command but no data will be written. The write cycle time must be observed even if write protection is enabled. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or `page size') and end at addresses that are integer multiples of [page size - 1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is therefore necessary that the application software prevent page write operations that would attempt to cross a page boundary.
6.2
Page Write
The write-control byte, word address and the first data byte are transmitted to the 24AA014/24LC014 in the same way as in a byte write. But instead of generating a Stop condition, the master transmits up to 15 additional data bytes to the 24AA014/24LC014 that are temporarily stored in the on-chip page buffer and will be written into the memory once the master has transmitted a Stop condition. Upon receipt of each word, the four lower order address pointer bits are internally incremented by one.
6.3
WRITE PROTECTION
The WP pin must be tied to VCC or VSS. If tied to VCC, the entire array will be write-protected. If the WP pin is tied to VSS, write operations to all address locations are allowed.
FIGURE 6-1:
S BUS ACTIVITY T A MASTER R T SDA LINE S BUS ACTIVITY
BYTE WRITE
CONTROL BYTE WORD ADDRESS DATA S T O P P A C K A C K A C K
FIGURE 6-2:
BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY S T A R T S
PAGE WRITE
CONTROL BYTE WORD ADDRESS (n) S T O P P A C K A C K A C K A C K A C K
DATA (n)
DATA (n +1)
DATA (n + 15)
2003 Microchip Technology Inc.
DS21809B-page 7
24AA014/24LC014
7.0 ACKNOWLEDGE POLLING
FIGURE 7-1:
Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a write command has been issued from the master, the device initiates the internally-timed write cycle and ACK polling can be initiated immediately. This involves the master sending a Start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, no ACK will be returned. If no ACK is returned, the Start bit and control byte must be resent. If the cycle is complete, the device will return the ACK and the master can then proceed with the next read or write command. See Figure 7-1 for a flow diagram of this operation.
ACKNOWLEDGE POLLING FLOW
Send Write Command
Send Stop Condition to Initiate Write Cycle
Send Start
Send Control Byte with R/W = 0
Did Device Acknowledge (ACK = 0)? Yes Next Operation
No
DS21809B-page 8
2003 Microchip Technology Inc.
24AA014/24LC014
8.0 READ OPERATIONS
Read operations are initiated in the same way as write operations, with the exception that the R/W bit of the slave address is set to `1'. There are three basic types of read operations: current address read, random read and sequential read. Once the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. The master then issues the control byte again but with the R/W bit set to a `1'. The 24AA014/24LC014 will then issue an acknowledge and transmits the eight-bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the 24AA014/24LC014 discontinues transmission (Figure 8-2). After this command, the internal address counter will point to the address location following the one that was just read.
8.1
Current Address Read
The 24AA014/24LC014 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to `1', the 24AA014/24LC014 issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the 24AA014/24LC014 discontinues transmission (Figure 8-1).
8.3
Sequential Read
Sequential reads are initiated in the same way as a random read except that after the 24AA014/24LC014 transmits the first data byte, the master issues an acknowledge as opposed to a Stop condition in a random read. This directs the 24AA014/24LC014 to transmit the next sequentially addressed 8-bit word (Figure 8-3). To provide sequential reads the 24AA014/24LC014 contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. The internal address pointer will automatically roll over from address 0FFh to address 000h.
8.2
Random Read
Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is done by sending the word address to the 24AA014/24LC014 as part of a write operation.
FIGURE 8-1:
CURRENT ADDRESS READ
S T BUS ACTIVITY A CONTROL MASTER BYTE R T SDA LINE S BUS ACTIVITY A C K S T O P P N O A C K
DATA
2003 Microchip Technology Inc.
DS21809B-page 9
24AA014/24LC014
FIGURE 8-2: RANDOM READ
S T CONTROL A BYTE R T S WORD ADDRESS (n) S T A CONTROL BYTE R T S A A C C K K S T O P P N O A C K
BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY
DATA (n)
A C K
FIGURE 8-3:
SEQUENTIAL READ
DATA (n) DATA (n + 1) DATA (n + 2) S T DATA (n + X) O P P N O A C K
BUS ACTIVITY CONTROL MASTER BYTE SDA LINE BUS ACTIVITY A C K
A C K
A C K
A C K
DS21809B-page 10
2003 Microchip Technology Inc.
24AA014/24LC014
9.0
9.1
PACKAGING INFORMATION
Package Marking Information
8-Lead PDIP (300 mil) XXXXXXXX T/XXXNNN YYWW Example: 24LC014 I/P12F 0321
8-Lead SOIC (150 mil) XXXXXXXX T/XXYYWW NNN
Example: 24LC014 I/SN0321 12F
8-Lead TSSOP XXXX TYWW NNN 8-Lead MSOP XXXXT YWWNNN
Part Number TSSOP/MSOP Marking Code
Example: 4L14 I321 12F Example: 4L14I 32112F
24AA014 24LC014
4A14 4L14
Legend: XX...X T YY WW NNN Note:
Customer specific information* Temperature grade (I,E) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
2003 Microchip Technology Inc.
DS21809B-page 11
24AA014/24LC014
8-Lead Plastic Dual In-line (P) - 300 mil (PDIP)
E1
D 2 n 1 E
A
A2
c
L A1
eB
B1 p B
Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB
MIN
INCHES* NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10
MAX
MIN
.140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5
.170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15
MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
MAX
4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018
DS21809B-page 12
2003 Microchip Technology Inc.
24AA014/24LC014
8-Lead Plastic Small Outline (SN) - Narrow, 150 mil (SOIC)
E E1
p
D 2 B n 1
h 45
c A A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D h L c B
MIN
.053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0
INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12
MAX
MIN
.069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15
MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12
MAX
1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057
2003 Microchip Technology Inc.
DS21809B-page 13
24AA014/24LC014
8-Lead Plastic Thin Shrink Small Outline (ST) - 4.4 mm (TSSOP)
E E1 p
D 2 1 n B
A c
L
A1
A2
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B
MIN
INCHES NOM 8 .026
MAX
MIN
.033 .002 .246 .169 .114 .020 0 .004 .007 0 0
.035 .004 .251 .173 .118 .024 4 .006 .010 5 5
.043 .037 .006 .256 .177 .122 .028 8 .008 .012 10 10
MILLIMETERS* NOM MAX 8 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 2.90 3.00 3.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-086
DS21809B-page 14
2003 Microchip Technology Inc.
24AA014/24LC014
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E E1
p D 2 B n 1
A c A1 (F)
A2
L
8 Number of Pins Pitch .026 BSC A .043 Overall Height A2 Molded Package Thickness .030 .033 .037 A1 .000 .006 Standoff E Overall Width .193 TYP. E1 .118 BSC Molded Package Width D .118 BSC Overall Length L .016 .024 .031 Foot Length Footprint (Reference) F .037 REF 0 8 Foot Angle c .003 .006 .009 Lead Thickness B .009 .012 .016 Lead Width 5 15 Mold Draft Angle Top 5 15 Mold Draft Angle Bottom *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side.
Units Dimension Limits n p
MIN
INCHES NOM
MAX
MIN
MILLIMETERS* NOM 8 0.65 BSC 0.75 0.85 0.00 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0.60 0.95 REF 0 0.08 0.22 5 5 -
MAX
1.10 0.95 0.15
0.80 8 0.23 0.40 15 15
JEDEC Equivalent: MO-187
Drawing No. C04-111
2003 Microchip Technology Inc.
DS21809B-page 15
24AA014/24LC014
APPENDIX A:
Revision B Corrections to Section 1.0, Electrical Characteristics.
REVISION HISTORY
DS21809B-page 16
2003 Microchip Technology Inc.
24AA014/24LC014
ON-LINE SUPPORT
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2003 Microchip Technology Inc.
DS21809B-page 17
24AA014/24LC014
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS21809B FAX: (______) _________ - _________
Device: 24AA014/24LC014 Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21809B-page 18
2003 Microchip Technology Inc.
24AA014/24LC014
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package Examples: a) b) c) 24AA014-I/P: Industrial Temperature, 1.8V, PDIP package. 24AA014-I/SN: Industrial Temperature, 1.8V, SOIC Package. 24AA014T-I/ST: Industrial Temperature, 1.8V, TSSOP Package, Tape and Reel 24LC014-I/P: Industrial Temperature, 2.5V, PDIP Package. 24LC014T-I/SN: Industrial Temperature, 2.5V, SOIC Package, Tape and Reel 24LC014T-I/MS: Industrial Temperature, 2.5V, MSOP Package, Tape and Reel.
Device:
24AA014: 1.8V, 1 Kbit Addressable Serial EEPROM 24AA014T: 1.8V, 1 Kbit Addressable Serial EEPROM (Tape and Reel) 24LC014: 2.5V, 1 Kbit Addressable Serial EEPROM 24LC014T: 2.5V, 1 Kbit Addressable Serial EEPROM (Tape and Reel)
a) b)
Temperature Range:
I
=
-40C to +85C
c)
Package: P SN ST MS = = = = Plastic DIP, (300 mil Body), 8-lead Plastic SOIC, (150 mil Body) TSSOP, 8-lead MSOP, 8-lead
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2003 Microchip Technology Inc.
DS21809B-page 19
24AA014/24LC014
NOTES:
DS21809B-page 20
2003 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
2003 Microchip Technology Inc.
DS21809B-page 21
WORLDWIDE SALES AND SERVICE
AMERICAS
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07/28/03
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DS21809B-page 22
2003 Microchip Technology Inc.

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